RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RPack: routability-driven packing for cluster-based FPGAs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Estimating Pre-Placement FPGA Interconnection Requirements
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
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The majority of networks subject to routing in almost every FPGA design consist of networks with only 2 to 4 terminals. These usually connect to directly adjacent logic cells. In order to make best use of this circumstance commercial FPGA architecture vendors provide dedicated local routing resources on the inter and intra logic block level. Previous routability-driven placement algorithms try to minimize utilization of global routing resources without taking local routing resources into account. This paper presents a new placement algorithm MPCPlace (Multipass Clustering and Placement) which makes specific use of local routing resources and hence reduces congestion on global routing resources and greatly improves overall routability in FPGA designs. The results obtained with the new placement algorithm will be compared to the SCPlace-Algorithm as well as the commercial Altera Quartus II software for various real world designs. The benchmark results at hand indicate for the new MPCPlace algorithm an average increase in routing resource utilization of up to 12.5% as well as a peak improvement of 10%.