Capacitor matching insensitive algorithmic ADC requiring no calibrations

Authors:
Patrick Quinn;Maxim Pribytko
Affiliations:
Xilinx Ireland, IC design, Citywest Business Campus, Logic Drive, Saggart, Dublin, Ireland;Xilinx Ireland, IC design, Citywest Business Campus, Logic Drive, Saggart, Dublin, Ireland
Venue:
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Year:
2003

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Cited 1

High-speed and low-power scalable Hamming weight comparator based on a non-weighted switched-capacitor array

Analog Integrated Circuits and Signal Processing

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Abstract

A novel implementation of the algorithmic ADC is proposed in this paper. The ADC is based on an algorithmic 1.5-bit stage in which voltage multiplication is replaced by voltage addition. A floating voltage hold circuit is proposed which enables the accurate addition of signal voltages without requiring precision components. An experimental 12 bit 3.3 MS/s algorithmic ADC in 0.25 µm standard CMOS is described. It occupies 0.15mm2 of die area and dissipates 5.5mW. The power and area FOMs are well below those previously reported for 1.5-bit stage algorithmic ADCs.