FPGA implementation of highly parallelized decoder logic for network coding (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Design and evaluation of random linear network coding Accelerators on FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
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Current generation of FPGAs with integrated high-speed transceivers provide a useful tool for prototyping various networking applications. We discuss a case study in developing a high-speed network interface card (NIC) for communication networks. The NIC implements a low-latency signaling protocol called Just-in-Time (JIT) for Optical Burst Switched networks. The main processing engine inside the FPGA runs at 62.5MHz and can handle data streams up to 1Gbps. The NIC utilizes the FPGA's gigabit transceiver cores, standard PCS/PMA and MAC layers and uses an optical front-end card to transmit data optically on specific wavelengths. The JIT engine in the NIC processes three kinds of messages - messages from the host, the network and internal timing messages associated with various timer events. The engine implements layer 3 functions typically implemented in software - like generating signaling messages and maintaining all active connections. This allows very fast setup and teardown of connections than otherwise possible.