MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
High-level design and validation of the BlueSPARC multithreaded processor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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This work is part of our on-going effort to prototype an Itanium microarchitecture on an FPGA. To conserve time and effort in model development, we described our microarchitecture in Bluespec, a synthesizable high-level hardware description language. The microarchitecture model currently supports a subset of the Itanium instruction set architecture (ISA). The model includes details such as multi-bundle instruction fetch, decode and issue, parallel pipelined execution units with scoreboarding and bypassing, and multiple levels of cache hierarchies. The microarchitecture model is synthesized and prototyped on an FPGA that interfaces directly to the memory bus of a host PC. The prototyped microprocessor core executes the supported ISA subset at 100MHz and directly references the host-PC's DRAM and I/O resources through the memory bus at up to 800MB/sec of bandwidth. This effort is a first step toward developing a convenient in-system microprocessor prototyping platform capable of executing realistic full-scale applications and operating systems.