Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Virtual Components Design and Reuse
Virtual Components Design and Reuse
Practical code coverage for Verilog
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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IP core reuse is necessary to overcome the design gap. Yet experience during IP integration has shown that risk is still considerably high when dealing with IPs. IP qualification provides IP providers and integrators with measurable quality characteristics that allow for high quality IPcores and to put buy decisions on a quantifiable basis. This paper presents unprecedented results that facilitate the comparison of the effectiveness of reusing qualified, digital soft IP to previous, immature reuse methods. An impressive reduction in IP integration effort, which is profitable for the IP customer, is demonstrated. Moreover, we show that the IP business can be profitable for the IP provider despite the additional qualification effort.