An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology

  • Authors:
  • Pallav Gupta;Niraj K. Jha

  • Affiliations:
  • -;-

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe - Volume 2
  • Year:
  • 2004

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Abstract

In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massivethroughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.