A fast and flexible performance simulator for micro-architecture trade-off analysis on UltraSPARC-I
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient simulation of trace samples on parallel machines
Parallel Computing
Optimal sample length for efficient cache simulation
Journal of Systems Architecture: the EUROMICRO Journal
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
IEEE Transactions on Computers
FaCSim: a fast and cycle-accurate architecture simulator for embedded systems
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Branch Predictor Warmup for Sampled Simulation through Branch History Matching
Transactions on High-Performance Embedded Architectures and Compilers II
Branch history matching: branch predictor warmup for sampled simulation
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Finding extreme behaviors in microprocessor workloads
Transactions on High-Performance Embedded Architectures and Compilers IV
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In order to quickly decide which architectural features are to be included in future processors, we have developed a simulation approach that uses samples of benchmark program instruction traces. Rather than simulating a proposed architecture on the entire SPEC92 program suite of more than 100 billion instructions, we simulate using a set of samples of the SPEC92 suite containing less than 1% of the total instruction trace. Each of our samples contains a relatively short instruction trace that can be simulated quickly. The technique described can be applied to existing architectural models to produce significant reductions in simulation time. Existing simulation tools can be leveraged to implement the trace sampling technique described.