Digital Technical Journal - Special 10th anniversary issue
A fast and flexible performance simulator for micro-architecture trade-off analysis on UltraSPARC-I
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance evaluation of the PowerPC 620 microarchitecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Emulation verification of the Motorola 68060
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Incas: a cycle accurate model of UltraSPARC
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Accelerating Architectural Simulation by Parallel Execution of Trace Samples
Accelerating Architectural Simulation by Parallel Execution of Trace Samples
The embedded Java benchmark suite JemBench
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
A full lifecycle performance verification methodology for multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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picoJava performance modeling and Validation use simulator checkpoints to speed Register Transfer Level (RTL) model simulation. In the process of designing high-performance microprocessors, architects and designers build processor models at varying levels of abstraction for a range of purposes, such as simulating and verifying the processor, predicting processor performance, and developing operating systems and applications for the processor before silicon is available. Such models can range in complexity, from simple analytical performance models in spreadsheet format to the detailed design expressed in a Hardware Description Language (HDL). Other models that fall in between on the range of complexity include instruction-accurate simulators, trace-driven performance simulators, and cycle-accurate simulators. There is usually a trade-off between runtime performance and accuracy while using these models.