Algorithms for automatic length compensation of busses in analog integrated circuits
Proceedings of the 2007 international symposium on Physical design
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Traces on printed circuit boards (PCBs) are often turned into meandering lines to introduce an additional delay. This technical report explores the electrical parasitics involved in that practice by reporting measurements of traces fabricated on a test board. Traces that meander have shorter propagation delays than expected due to coupling between segments. Calculations of the time delay reduction are presented and a model is proposed.