An Efficient Reconfigurable Architecture and Implementation of Edge Detection Algorithm using Handle-C

  • Authors:
  • Daggu Venkateshwar Rao;Muthukumar Venkatesan

  • Affiliations:
  • -;-

  • Venue:
  • ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
  • Year:
  • 2004

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Abstract

Computer manipulation of images is generallydefined as Digital Image Processing (DIP). DIPis employed in variety of applications, includingvideo surveillance, target recognition, and imageenhancement. Some of the algorithms used inimage processing include convolution, edgedetection and contrast enhancement. These areusually implemented in software but may also beimplemented in special purpose hardware toreduce speed. In this work the canny edgedetection [A computational approach to edge detection] architecture has been developedusing reconfigurable architecture and hardwaremodeled using a C-like hardware languagecalled Handle-C. The proposed architecture iscapable of producing one edge-pixel every clockcycle. The hardware modeled was implementedusing the DK2 IDE tool on the RC1000 XilinxVertex FPGA based board [Introduction software paradigms to hardware design]. The algorithm was tested on standard image processingbenchmarks and significances of the result are discussed.