Compact floor-planning via orderly spanning trees

Authors:
Chien-Chih Liao;Hsueh-I Lu;Hsu-Chun Yen
Affiliations:
Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, Republic of China;Institute of Information Science, Academia Sinica, Taipei 115, Taiwan, Republic of China;Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, Republic of China
Venue:
Journal of Algorithms
Year:
2003

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Abstract

Floor-planning is a fundamental step in VLSI chip design. Based upon the concept of orderly spanning trees, we present a simple O(n)-time algorithm to construct a floor-plan for any n-node plane triangulation. In comparison with previous floor-planning algorithms in the literature, our solution is not only simpler in the algorithm itself, but also produces floor-plans which require fewer module types. An equally important aspect of our new algorithm lies in its ability to fit the floorplan area in a rectangle of size (n - 1) × ⌊(2n + 1)/3⌋. Lower bounds on the worst-case area for floor-planning any plane triangulation are also provided in the paper.