Flexible architectures for engineering successful SOCs

Authors:
Chris Rowen;Steve Leibson
Affiliations:
Tensilica, Inc., San Jose, CA;Tensilica, Inc., San Jose, CA
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

Citing 0
Cited 5

Designing real-time H.264 decoders with dataflow architectures

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip

Proceedings of the conference on Design, automation and test in Europe
Understanding sources of inefficiency in general-purpose chips

Proceedings of the 37th annual international symposium on Computer architecture
Understanding sources of ineffciency in general-purpose chips

Communications of the ACM
SWSL: software synthesis for network lookup

ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems

Quantified Score

Hi-index	0.03

Visualization

Abstract

This paper focuses on a particular SOC design technology and methodology, here called the advanced or processor-centric SOC design method, which reduces the risk of SOC design and increases ROI by using configurable processors to implement on-chip functions while increasing the SOC's flexibility through software programmability. The essential enabler for this design methodology is automatic processor generation-the rapid and easy creation of new microprocessor architectures, complete with efficient hardware designs and comprehensive software tools. The high speed of the generation process and the great flexibility of the generated architectures underpin a fundamental shift of the role of processors in system architecture.