High-speed local area networks and their performance: a survey
ACM Computing Surveys (CSUR)
Modeling, synthesis, and rapid prototyping with the verilog HDL
Modeling, synthesis, and rapid prototyping with the verilog HDL
The Winn L. Rosch Hardware Bible with Cdrom
The Winn L. Rosch Hardware Bible with Cdrom
80x86 IBM PC and Compatible Computers: Assembly Language, Design and Interfacing
80x86 IBM PC and Compatible Computers: Assembly Language, Design and Interfacing
Wideband Networking
EMP: zero-copy OS-bypass NIC-driven gigabit ethernet message passing
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
Experience in Offloading Protocol Processing to a Programmable NIC
CLUSTER '02 Proceedings of the IEEE International Conference on Cluster Computing
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient Layering for High Speed Communication: Fast Messages 2.x
HPDC '98 Proceedings of the 7th IEEE International Symposium on High Performance Distributed Computing
Using Embedded Network Processors to Implement Global Memory Management in a Workstation Cluster
HPDC '99 Proceedings of the 8th IEEE International Symposium on High Performance Distributed Computing
Integrating firewire peripheral interface with an ethernet custom network processor
Integration, the VLSI Journal
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In this paper, we present the design and synthesis of "Direct Connected Device Core" (DCD-Core) as a low cost and low power consumption embedded system, which includes an electrical erasable programmable read only memory (EEPROM) controller for configurable address assignments. The main function of DCD-embedded system is to eliminate the operating system processing of network protocol stack running by personal computers CPU and simplifying network connection requirements. Not only the hardware solution requires connection simplification, but also it improves network performance. Our DCD-Core utilizes the concept of network channels, where Ethernet frames are delivered through a custom multicast addressing scheme. After validating DCD-Core embedded system simulation outputs, we synthesize the design in FPGA chip using Verilog Hardware Description Language (HDL). Performance measures like power consumption and area utilization are computed using Verilog HDL synthesis tools. Initial performance measures had shown that the DCD-Core reduces the power consumption. Thus, network devices may be powered through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. This way, DCD-Core reduces the connection complexity in terms of device installations, especially for large number of devices (e.g. surveillance system cameras).