Performance modelling with the formal specification language SDL
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Schedulability analysis of heterogeneous systems for performance message sequence chart
Proceedings of the 6th international workshop on Hardware/software codesign
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Timing Constraints in Message Sequence Chart Specifications
FORTE X / PSTV XVII '97 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE X) and Protocol Specification, Testing and Verification (PSTV XVII)
An Analyser for Mesage Sequence Charts
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Specification and simulation of real time concurrent systems using standard SDL tools
SDL'03 Proceedings of the 11th international conference on System design
SDL'03 Proceedings of the 11th international conference on System design
An extension for MSC-2000 and its application
SAM'02 Proceedings of the 3rd international conference on Telecommunications and beyond: the broader applicability of SDL and MSC
International Journal of Mobile Communications
Designing distributed software with RT-CORBA and SDL
Computer Standards & Interfaces
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The correctness of hard real-time systems depends not only on the correct functional behavior but also on the correct temporal behavior. That is, the designed hard real-time system should meet all its functional and timing requirements even in the worst case. By performing timing analysis in early stages of the system life cycle, it is possible to reduce the overall development costs. This is due to the fact that the detection of the deadline violation in hard real-time systems will often lead to a complete redesign. Therefore the integration of system specification and timing analysis will be very helpful in the design of hard real-time systems. In this paper a method is proposed which supports both functional and timing verification of the specified system. The method integrates the extended specification and description language (SDL) and message sequence chart (MSC) specifications with the task allocation and schedulability analysis algorithms. The extensions of SDL and MSC are annotations in form of embedded comments in the original languages. They are used to describe the timing requirements of the specified system. The usability of the proposed method is illustrated through a case study.