Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Spanning tree based state encoding for low power dissipation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Using dynamic cache management techniques to reduce energy in a high-performance processor
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Low-power memory mapping through reducing address bus activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler-directed proactive power management for networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ACM Transactions on Embedded Computing Systems (TECS)
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We present an algorithm for compiler-driven register name adjustmentwith the main goal of power minimization on instruction fetchand register file access. In most instruction set architecture (ISA) designs,the register fields reside in fixed positions within the instructionencoding, hence forming streams of indices on the instruction bus andto the register file address decoder. The number of bit transitions inthese streams greatly determines the power consumption on the addressbus and the register file decoder. While general-purpose registersare semantically indistinguishable and hence interchangeable,the particular register indices do have a direct impact on power consumption.The algorithms presented in this paper address this powerminimization problem by reassigning/encoding the registers so thatthe bit transitions within the register index streams are minimized.