High Speed Homology Search Using Run-Time Reconfiguration
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign
CSB '03 Proceedings of the IEEE Computer Society Conference on Bioinformatics
FPGA-based communications receivers for smart antenna array embedded systems
EURASIP Journal on Embedded Systems
DNA Physical Mapping on a Reconfigurable Platform
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
High performance phylogenetic analysis with maximum parsimony on reconfigurable hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accelerating motif discovery: motif matching on parallel hardware
WABI'06 Proceedings of the 6th international conference on Algorithms in Bioinformatics
A parallel cooperative team of multiobjective evolutionary algorithms for motif discovery
The Journal of Supercomputing
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Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this platform, a microprocessor is immersed into field programmable gate array (FPGA) fabric for realizing an effective environment for HW/SW co-design implementation. Significant improvements in data transmission between hardware and software and higher clock frequency of FPGA have been realized when compared to the JBits interface in the previous design. In addition, the embedded platform provides a greater flexibility in partitioning hardware and software tasks. These new features lead to much faster computation speed for phylogeny inference. In this paper, the architecture for HW/SW co-design in the embedded platform is presented. The FPGA logic design for the tree likelihood evaluation has also been improved to tackle problem of larger scale by adopting the idea of partial likelihood.