FPGA Implementations of the Massively Parallel GCA Model
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
A scalable configurable architecture for the massively parallel GCA model
International Journal of Parallel, Emergent and Distributed Systems - Advances in Parallel and Distributed Computational Models
The GCA-w Massively Parallel Model
PaCT '09 Proceedings of the 10th International Conference on Parallel Computing Technologies
Solving the exploration's problem with several creatures more efficiently
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
Optimal 6-state algorithms for the behavior of several moving creatures
ACRI'06 Proceedings of the 7th international conference on Cellular Automata for Research and Industry
Are several creatures more efficient than a single one?
ACRI'06 Proceedings of the 7th international conference on Cellular Automata for Research and Industry
parallel hardware architecture to simulate movable creatures in the CA model
PaCT'07 Proceedings of the 9th international conference on Parallel Computing Technologies
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The GCA (Global Cellular Automata) model is a very interesting model which can be used to implement all kind of parallel problems. The GCA model consists of a field of cells as in the Cellular Automata model. Each cell has links to a set of remote cells which can be dynamically changed from generation to generation. A cell reads the remote neighbour's states and then changes its own state according to a local rule. The model is massively parallel because all cells can change their states independently in parallel. We have investigated how the GCA model can be implemented efficiently in hardware using a FPGA prototyping platform. We have implemented a fully parallel architecture where all cells really operate in parallel and another architecture where the cells are stored in memories in order to handle a large number of cells. We are showing that in the fully parallel architecture a speed-up of more than 3000 compared to a software implementation on a PC is realistic on a modern FPGA platform. In the partially parallel architecture based on memories the speed-up will be lower but the number of cells is only restricted by the capacity of the memories.