A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding

Authors:
Grzegorz Pastuszak
Affiliations:
Warsaw University of Technology, Poland
Venue:
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Year:
2004

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Abstract

This paper presents a high-performance architecture of the context adaptive binary arithmetic coder (CABAC) for the embedded block-coding algorithm in JPEG 2000. The architecture has been developed in two variants to code two or three context-symbol pairs per clock cycle. The inverse multiple branch selection (IMBS) method is proposed to minimize critical paths, which originate from causally dependent operations. The designs have been implemented in VHDL and synthesized for FPGA devices. Simulation results show that the two- and three-symbol engines can process about 22 million samples at 77 and 53 MHz working frequency, respectively.