Systematic Debugging of Real-Time Systems based on Incremental Satisfiability Counting

Authors:
Stefan Andrei;Albert M. K. Cheng;Wei-Ngan Chin;Miahi Lupu
Affiliations:
National University of Singapore;University of Houston;National University of Singapore;National University of Singapore
Venue:
RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
Year:
2005

Citing 0
Cited 2

Automatic Debugging of Real-Time Systems Based on Incremental Satisfiability Counting

IEEE Transactions on Computers
Ji.Fi: visual test and debug queries for hard real-time

Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Real-time logic (RTL) is useful for the verification of a safety assertion with respect to the specification of a real-time system. Since the satisfiability problem for RTL is undecidable, the systematic debugging of a real-time system appears impossible. This paper provides a first step towards this challenge. With RTL, each propositional formula corresponds to a verification condition. The number of truth assignments of a propositional formula helps to determine the timing constraints which should be added or modified to the system's specification. We have implemented a tool (called SDRTL) that is able to perform systematic debugging. The confidence of our approach is high as we have evaluated SDRTL on several existing industrial-based applications.