Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips
Journal of Computer Science and Technology
A combined arithmetic logic unit and memory element for the design of a parallel computer
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
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Vendors are revisiting an old concept--the clockless chip--as they look for new processorapproaches to work with the growing number of cellular phones, PDAs, and other high performance, battery-powered devices.