Pattern matching in reconfigurable logic for packet classification
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Content addressable memories are important components in high-speed networking equipment. This paper describes the design of a wide CAM suitable for use as an IPv6 traffic classifier for a 622Mb/s communications link. The design flow uses a combination of standard design tools in conjunction with JBits, a low-level configuration API for manipulating programmable resources. The CAMs are 320 bits wide to accommodate a full IPv6 header. The most powerful wildcarding possible is supported, ranging from donýt cares on single bits of the header, all the way through to donýt cares for the whole header. A priority mechanism has been designed which allows explicit priority encoding to be used without required a costly sorting network. This is performed by dynamic routing, whereby routes are determined at run-time between the match units and the priority encoder. This allows a smaller, faster implicit priority encoder to be used, whilst still allowing priority to be explicitly defined. An experimental set-up is shown, which allows 128 320-bit patterns to be matched at 50.9 Msearches/s.