Pattern matching in reconfigurable logic for packet classification

Authors:
Adam Johnson;Kenneth Mackenzie
Affiliations:
Georgia Institute of Technology, Atlanta, GA;Georgia Institute of Technology, Atlanta, GA
Venue:
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Year:
2001

Citing 6
Cited 2

Packet classification using tuple space search

Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification on multiple fields

Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Scalable packet classification

Proceedings of the 2001 conference on Applications, technologies, architectures, and protocols for computer communications
The Density Advantage of Configurable Computing

Computer
An Efficient Content-Addressable Memory Implementation Using Dynamic Routing

FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Rapid Synthesis of Pattern Classification Circuits

FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

TCP Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware

IEEE Micro
An overview of reconfigurable hardware in embedded systems

EURASIP Journal on Embedded Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

We describe a digital circuit synthesis algorithm specialized for the domain of pattern matching circuits implemented in reconfigurable logic. We propose to use this algorithm as part of a system for implementing high-throughput pattern classification, for instance as part of a packet filter in an internetwork router. The goals of the approach are throughputs on the order of 100M classifications per second with reconfiguration times (including all synthesis) being held to a minimum.We evaluate the algorithms using rulesets from a pattern classification problem in networking, IP firewalling (150 rules on 100 bits), and evaluate their fitness to handle the demands placed on them by high-speed networks. In addition we use synthetic rulesets in an attempt to explore the scalability of our algorithm.