Pattern matching in reconfigurable logic for packet classification
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
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We describe digital circuit synthesis and placement algorithms specialized for the domain of pattern matching circuits implemented in reconfigurable logic. We propose to use these algorithms as part of a system for implementing high-throughput pattern classification, for instance as part of a packet filter in a internetwork router. The goals of the approach are throughputs on the order of 100M classifications per second with reconfiguration times (including all synthesis) on the order of 10 seconds. We evaluate the algorithms using rulesets from two pattern classification problems in networking: IP routing (41,000 rules on 32 bits) and IP firewalling (180 rules on 100 bits) and compare their performance against standard tools. We find that the fast synthesis tools suffer about a 2脳 increase in circuit size but achieve substantial speedups over standard tools.