Data partitioning-based parallel irregular reductions: Research Articles

  • Authors:
  • Eladio Gutiérrez;Oscar Plata;Emilio L. Zapata

  • Affiliations:
  • Department of Computer Architecture, University of Malaga, E-29071 Malaga, Spain;Department of Computer Architecture, University of Malaga, E-29071 Malaga, Spain;Department of Computer Architecture, University of Malaga, E-29071 Malaga, Spain

  • Venue:
  • Concurrency and Computation: Practice & Experience - Compilers for Parallel Computers
  • Year:
  • 2004

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Abstract

Different parallelization methods for irregular reductions on shared memory multiprocessors have been proposed in the literature in recent years. We have classified all these methods and analyzed them in terms of a set of properties: data locality, memory overhead, exploited parallelism, and workload balancing. In this paper we propose several techniques to increase the amount of exploited parallelism and to introduce load balancing into an important class of these methods. Regarding parallelism, the proposed solution is based on the partial expansion of the reduction array. Load balancing is discussed in terms of two techniques. The first technique is a generic one, as it deals with any kind of load imbalance present in the problem domain. The second technique handles a special case of load imbalance which occurs whenever a large number of write operations are concentrated on small regions of the reduction arrays. Efficient implementations of the proposed optimizing solutions for a particular method are presented, experimentally tested on static and dynamic kernel codes, and compared with other parallel reduction methods. Copyright © 2004 John Wiley & Sons, Ltd.