Modalities for model checking: branching time logic strikes back
Science of Computer Programming
Design and validation of computer protocols
Design and validation of computer protocols
Handbook of theoretical computer science (vol. B)
Memory-efficient algorithms for the verification of temporal properties
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Software quality: a framework for success in software development and support
Software quality: a framework for success in software development and support
The chaining approach for software test data generation
ACM Transactions on Software Engineering and Methodology (TOSEM)
A new scheme for memory-efficient probabilistic verification
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Model checking
Fundamenta Informaticae - Special issue on Concurrency specification and programming (CS&P)
Formal Analysis of a Space-Craft Controller Using SPIN
IEEE Transactions on Software Engineering
On the Verification of Temporal Properties
Proceedings of the IFIP TC6/WG6.1 Thirteenth International Symposium on Protocol Specification, Testing and Verification XIII
Faster Algorithms for the Nonemptiness of Streett Automata and for Communication Protocol Pruning
SWAT '96 Proceedings of the 5th Scandinavian Workshop on Algorithm Theory
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
On-the-Fly Verification with Stubborn Sets
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
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We present a new memory efficient algorithm for on-the-fly verification of labelled transition systems (LTSs) with testers. To our knowledge, this is the first thoroughly presented solution for verifying all properties specifiable with testers. The algorithm requires four passes of the state space of the composition of the LTS and the tester.