Template-driven parasitic-aware optimization of analog integrated circuit layouts

Authors:
Sambuddha Bhattacharya;Nuttorn Jangkrajarng;C-J. Richard Shi
Affiliations:
University of Washington, Seattle, WA;University of Washington, Seattle, WA;University of Washington, Seattle, WA
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

Citing 2
Cited 1

Correct-by-construction layout-centric retargeting of large analog designs

Proceedings of the 41st annual Design Automation Conference
Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits

Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

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Abstract

Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated circuits. In order to ensure desired circuit performance, bounds on layout parasitics' magnitudes are determined first. Then, graph techniques are coupled with mathematical programming to constrain layout geometry based on these parasitic bounds. The algorithm has been demonstrated to ensure desired circuit performance during technology migration and performance specification changes.