A Low Power Embedded Dataflow Coprocessor

Authors:
Yijun Liu;Steve Furber
Affiliations:
University of Manchester;University of Manchester
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

Citing 2
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International Journal of High Performance Systems Architecture

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Abstract

Power consumption has become one of the most important concerns in microprocessor design. However, the potential for further power-saving in microprocessors with a conventional architecture is limited because of theirunified architectures and mature low-power techniques. An alternative way is proposed in this paper to save power 驴 embedding a dataflow coprocessor in a conventional RISC processor. The dataflow coprocessor is designed to execute short code segments very efficiently. The primary experimental results show that the dataflow coprocessor can increase the power efficiency of a RISC processor by an order of magnitude.