RG-SRAM: A Low Gate Leakage Memory Design

Authors:
Charan Thondapu;Praveen Elakkumanan;Ramalingam Sridhar
Affiliations:
State University of New York at Buffalo;State University of New York at Buffalo;State University of New York at Buffalo
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

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Abstract

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel Reduced-Gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in Very Deep Sub-Micron (VDSM) cache and embedded memories.