Focusing processor policies via critical-path prediction
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Reducing power with dynamic critical path information
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Power and Performance Fitting in Nanometer Design
IWIA '02 Proceedings of the International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02)
Dynamic Prediction of Critical Path Instructions
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Energy-efficient instruction scheduling utilizing cache miss information
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
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In recent years, advanced applications that require high processing performance are executed on portable and mobile devices. Those devices require high-performance and low-power processors. To satisfy this requirement, we propose to exploit information regarding instruction criticality. In order to reduce energy consumption with maintaining high performance, each functional units in our processor has different latency and energy consumption. This paper describes the best combination of functional units for the criticality-based low-power processor. The evaluated results show two fast and four slow combination is the best, when the total number of its functional units is six.