Architectural Characterization of TCP/IP Packet Processing on the Pentium® M Microprocessor

  • Authors:
  • Srihari Makineni;Ravi Iyer

  • Affiliations:
  • Intel Corporation;Intel Corporation

  • Venue:
  • HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
  • Year:
  • 2004

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Abstract

A majority of the current and next generation server applications (web services, e-commerce, storage, etc.) employ TCP/IP as the communication protocol of choice. As a result, the performance of these applications is heavily dependent on the efficient TCP/IP packet processing within the termination nodes. This dependency becomes even greater as the bandwidth needs of these applications grow from 100 Mbps to 1Gbps to 10Gbps in the near future. Motivated by this, our work presented in this paper focuses on the following: (a) to understand the performance behavior of the various modes of TCP/IP processing, (b) to analyze the underlying architectural characteristics of TCP/IP packet processing and (c) to quantify the computational requirements of the TCP/IP packet processing component within realistic workloads. We achieve these goals by performing an in-depth analysis of packet processing performance on Intelýs state-of-the-art low power Pentium® M microprocessor running the Microsoft Windows* Server 2003 operating system. Some of our key observations are 驴(i) that the mode of TCP/IP operation can significantly affect the performance requirements, (ii) that transmit-side processing is largely computeintensive as compared to receive-side processing which is more memory-bound and (iii) that the computational requirements for sending/receiving packets can form a substantial component (28% to 40%) of commercial server workloads. From our analysis, we also discuss architectural as well as stack-related improvements that can help achieve higher server network throughput and result in improved application performance.