Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Standby power management for a 0.18μm microprocessor
Proceedings of the 2002 international symposium on Low power electronics and design
A low power SRAM architecture based on segmented virtual grounding
Proceedings of the 2006 international symposium on Low power electronics and design
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SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse bias techniques for leakage reduction are implemented in a 2MByte SRAM testchip built with low power 90nm technology. Sophisticated analog regulators were implemented to precisely control the PMOS and NMOS reverse bias levels. The application of the reverse bias led to a 16X reduction in total array standby leakage and a cell leakage of only 20pA/bit. Excellent data retention for these bias conditions was demonstrated with detailed Vccmin mesurements