Enhancement of fault injection techniques based on the modification of VHDL code
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-error resilience of the IBM POWER6 processor
IBM Journal of Research and Development
Architecture Design for Soft Errors
Architecture Design for Soft Errors
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Hadrons generated by the primary cosmic rays penetrating the atmosphere have a negative impact on the reliability of semiconductor devices. The electrical charge induced by high energy particles manifests as a current spike and can affect both storage elements and combinational logic. Frequency of occurrence of the errors induced by this failure mechanism is referred to as soft error rate (SER). Continuous shrinking of the electronic devices and the lower supply voltages, in conjunction with the increased complexity of VLSI circuits, have led to higher SER. The impact of semiconductor technology scaling on neutron induced SER is discussed in this report. The experimental methodology and results of accelerated measurements carried out on Intel Itanium® microprocessors, at Los Alamos Neutron Science Center (LANSCE), are presented. Statistically significant values of the MTTF induced by high-energy neutrons are also derived, as a function of the number of upsets observed over the duration of the experiment. The presented approach doesnýt require any proprietary data about the microprocessor under evaluation and, as a consequence, can be used as a dependability benchmarking tool both by manufacturers and independent evaluators.