PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
The parallel execution of DO loops
Communications of the ACM
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
Optimal loop parallelization for maximizing iteration-level parallelism
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding
ACM Transactions on Embedded Computing Systems (TECS)
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Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP)applications.It is important to study effective and efficient transformation techniques to increase parallelism for nested loops.In this paper, we propose a novel technique,iterational retiming,that can satisfy any given timing constraint by achieving full parallelism for iterations in a partition. Theorems and efficient algorithms are proposed for iterational retiming. The experimental results show that iterational retiming is a promising technique for parallel embedded systems.It can achieve 87% improvement over software pipelining and 88%improvement over loop unfolding on average.