Optimal loop parallelization for maximizing iteration-level parallelism

  • Authors:

  • Duo Liu;Zili Shao;Meng Wang;Minyi Guo;Jingling Xue

  • Affiliations:

  • The Hong Kong Polytechnic University, Hung Hom, Hong Kong;The Hong Kong Polytechnic University, Hung Hom, Hong Kong;The Hong Kong Polytechnic University, Hung Hom, Hong Kong;Shanghai Jiao Tong University, Shanghai, China;The University of New South Wales, Sydney, Australia

  • Venue:
  • CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
  • Year:
  • 2009

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Abstract

This paper solves the open problem of extracting the maximal number of iterations from a loop that can be executed in parallel on chip multiprocessors. Our algorithm solves it optimally by migrating the weights of parallelism-inhibiting dependences on dependence cycles in two phases. First, we model dependence migration with retiming and formulate this classic loop parallelization into a graph optimization problem, i.e., one of finding retiming values for its nodes so that the minimum non-zero edge weight in the graph is maximized. We present our algorithm in three stages with each being built incrementally on the preceding one. Second, the optimal code for a loop is generated from the retimed graph of the loop found in the first phase. We demonstrate the effectiveness of our optimal algorithm by comparing with a number of representative non-optimal algorithms using a set of benchmarks frequently used in prior work.