An empirical evaluation of coding methods for multi-symbol alphabets
Information Processing and Management: an International Journal - Special issue: data compression
The data compression book (2nd ed.)
The data compression book (2nd ed.)
A Corpus for the Evaluation of Lossless Compression Algorithms
DCC '97 Proceedings of the Conference on Data Compression
The Z-Coder Adaptive Binary Coder
DCC '98 Proceedings of the Conference on Data Compression
IBM Journal of Research and Development
Low bit-rate speech coders for multimedia communication
IEEE Communications Magazine
An adaptive multialphabet arithmetic coding for video compression
IEEE Transactions on Circuits and Systems for Video Technology
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Modeling sequences of user actions for statistical goal recognition
User Modeling and User-Adapted Interaction
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This paper presents a practical realization in hardware of the concepts of variable order Markov modeling using multisymbol alphabets and arithmetic coding for lossless compression of universal data. This type of statistical coding algorithm has long been regarded as being able to deliver very high compression ratios close to the information content of the source data. However, their high computational complexity has limited their practical application in embedded environments such as in mobile computing and wireless communications. In this paper, a hardware amenable algorithm named PPMH and based on these principles has been developed and its architecture and implementation detailed. This novel lossless compression core offers innovative solutions to the computational issues in both stages of modeling and coding and delivers high compression efficiency and throughput. The configurability features of the core allow efficient use of the embedded SRAM present in modern FPGA technologies where memory resources range from a few kilobits to several megabits per device family. The core has been targeted to the Altera Stratix FPGA family and performance, coding efficiency, and complexity measured for different memory configurations.