Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor

  • Authors:

  • Toru Asano;Joel Silberman;Sang H. Dhong;Osamu Takahashi;Michael White;Scott Cottier;Takaaki Nakazato;Atsushi Kawasumi;Hiroshi Yoshihara

  • Affiliations:

  • IBM Engineering and Technology Services;IBM T.J. Watson Research Center;IBM Systems and Technology Group;IBM Systems and Technology Group;IBM Systems and Technology Group;IBM T.J. Watson Research Center;Toshiba Semiconductor Company;Toshiba Semiconductor Company;Sony Computer Entertainment of America

  • Venue:
  • IEEE Micro
  • Year:
  • 2005

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Abstract

The Synergistic Processor Element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a private or scratch pad memory. Such a memory is simple and needs to be high-frequency and large space in low-power. This design uses an 11 fan-out of four (11F04), six-cycle, fully pipelined, embedded 256-Kbyte SRAM for this purpose. The design's memory is not one hard macro, but a group of custom macros physically distributed to optimize the pipeline.