A fast algorithm to calculate the Euler number for binary images
Pattern Recognition Letters
Digital image processing
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Parallel computation of the Euler number via connectivity graph
Pattern Recognition Letters
Run-Based Algorithms for Binary Image Analysis and Processing
IEEE Transactions on Pattern Analysis and Machine Intelligence
Reflectance based object recognition
International Journal of Computer Vision
Image difference threshold strategies and shadow detection
BMVC '95 Proceedings of the 1995 British conference on Machine vision (Vol. 1)
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Digital Image Processing
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Digital Picture Processing
A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
ICPR '00 Proceedings of the International Conference on Pattern Recognition - Volume 3
Euler Vector: A Combinatorial Signature for Gray-Tone Images
ITCC '02 Proceedings of the International Conference on Information Technology: Coding and Computing
Pipeline architectures for recursive morphological operations
IEEE Transactions on Image Processing
Stacked Euler Vector (SERVE): A Gray-Tone Image Feature Based on Bit-Plane Augmentation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Archival image indexing with connectivity features using randomized masks
Applied Soft Computing
Computation of the Euler number using the contact perimeter
Computers & Mathematics with Applications
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Euler number of a binary image is a fundamental topological feature that remains invariant under translation, rotation, scaling, and rubber-sheet transformation of the image. In this work, a run-based method for computing Euler number is formulated and a new hardware implementation is described. Analysis of time complexity and performance measure is provided to demonstrate the efficiency of the method. The sequential version of the proposed algorithm requires significantly fewer number of pixel accesses compared to the existing methods and tools based on bit-quad counting or quad-tree, both for the worst case and the average case. A pipelined architecture is designed with a single adder tree to implement the algorithm on-chip by exploiting its inherent parallelism. The architecture uses O(N) 2-input gates and requires O(NlogN) time to compute the Euler number of an N × N image. The same hardware, with minor modification, can be used to handle arbitrarily large pixel matrices. A standard cell based VLSI implementation of the architecture is also reported. As Euler number is a widely used parameter, the proposed design can be readily used to save computation time in many image processing applications.