Application analysis using memory pressure

  • Authors:

  • Kartik Sudeep;Ahmed Gheith

  • Affiliations:

  • IBM Research, Austin Research Laboratory, Austin, TX;IBM Research, Austin Research Laboratory, Austin, TX

  • Venue:
  • Proceedings of the 2005 workshop on Memory system performance
  • Year:
  • 2005

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Abstract

As the speeds of microprocessors continue to follow Moore's law, memory speeds keep lagging farther behind so as to make the "memory wall" more and more distinct. In order for a processor architect to be able to evaluate the right micro-architectural features for the design, a study of the memory behavior of the applications becomes essential. In this paper we present a new metric termed "memory pressure" that can be used to analyze the application's behavior and quantify the demand an application places on the memory subsystem. Memory pressure is characterized by four metrics: (1) value-computation-to-use delay, (2)condition-resolution-to-use delay, (3) address-computation-to-use delay, and (4) value-load-to-use delay. It acts as an indicator of the opportunity that caching, prefetching, speculative loads or other DRAM latency hiding techniques can provide to improve the performance of the application. We have analyzed a few synthetic benchmarks as well as a few scientific applications and have been able to identify the benefit of caches and prefetch techniques for these benchmarks. As we demonstrate in this paper, quantifying the memory pressure not only provides insight into which architectural features a designer should evaluate for optimal performance, but also provides tangible hints to the software designer to make changes to the application -- algorithmic and structural -- to improve the performance.