Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks
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MisSPECulation: partial and misleading use of SPEC CPU2000 in computer architecture conferences
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Combining compiler and runtime IPC predictions to reduce energy in next generation architectures
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Deconstructing Commodity Storage Clusters
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Generating cache hints for improved program efficiency
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Application analysis using memory pressure
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A PAB-based multi-prefetcher mechanism
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Explicit control a batch-aware distributed file system
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Partial resolution for redundant operation table
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Efficient data structures for sparse network representation
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Investigating the impact of code generation on performance characteristics of integer programs
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RDVIS: a tool that visualizes the causes of low locality and hints program optimizations
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part II
A coldness metric for cache optimization
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The SPEC CPU2000 benchmark suite (http://www.spec.org/osg/cpu2000) is a collection of 26 compute-intensive, non-trivial programs used to evaluate the performance of a computer's CPU, memory system, and compilers. The benchmarks in this suite were chosen to represent real-world applications, and thus exhibit a wide range of runtime behaviors. On this webpage, we present functional cache miss ratios and related statistics for selected benchmarks in the SPEC CPU2000 suite. In particular, split L1 cache sizes ranging from 4KB to 1MB with 64B blocks and associativities of 1, 2, 4, 8 and full. Most of this data was collected at the University of Wisconsin-Madison with the aid of the Simplescalar toolset (http://www.simplescalar.org).