Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
The parallel graph reduction machine, Alice
Proc. of a workshop on Graph reduction
Randomized parallel communications on an extension of the omega network
Journal of the ACM (JACM)
Performance modelling of parallel computer architectures
SIGMETRICS '86/PERFORMANCE '86 Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation
Open, Closed, and Mixed Networks of Queues with Different Classes of Customers
Journal of the ACM (JACM)
The Distribution of Queuing Network States at Input and Output Instants
Journal of the ACM (JACM)
Decomposing Banyan Networks for Performance Analysis
IEEE Transactions on Computers
General Closed Queueing Networks with Blocking
Performance '87 Proceedings of the 12th IFIP WG 7.3 International Symposium on Computer Performance Modelling, Measurement and Evaluation
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
ALICE a multi-processor reduction machine for the parallel evaluation CF applicative languages
FPCA '81 Proceedings of the 1981 conference on Functional programming languages and computer architecture
Request Resubmission in a Blocking, Circuit-Switched, Interconnection Network
IEEE Transactions on Computers
ICDCIT'11 Proceedings of the 7th international conference on Distributed computing and internet technology
Queuing network of scale free topology: on modelling large scale network
The Journal of Supercomputing
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A major component of a parallel machine is its interconnection network (IN), which provides concurrent communication between the processing elements. It is common to use a multistage interconnection network (MIN) that is constructed using crossbar switches and introduces contention not only for destination addresses but also for internal links. Both types of contention are increased when nonlocal communication across a MIN becomes concentrated on a certain destination address, the hot-spot. This paper considers analytical models of asynchronous, circuit-switched INs in which partial paths are held during path building, beginning with a single crossbar and extending recursively to MINs. Since a path must be held between source and destination processors before data can be transmitted, switching networks are passive resources and queuing networks that include them do not therefore have product-form solutions. Using decomposition techniques, the flow-equivalent server (FES) that represents a bank of devices transmitting through a switching network is determined, under mild approximating assumptions. In the case of a full crossbar, the FES can be solved directly and the result can be applied recursively to model the MIN. Two cases are considered: one in which there is uniform routing and the other where there is a hot-spot at one of the output pins. Validation with respect to simulation for MINs with up to six stages (64-way switching) indicated a high degree of accuracy in the models.