Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation

Authors:
Florent Berthelot;Fabienne Nouvel
Affiliations:
CNRS UMR 6164 IETR-INSA, France;CNRS UMR 6164 IETR-INSA, Rennes, France
Venue:
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Year:
2006

Citing 0
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Abstract

Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture process. We present a method which generates automatically the design for both partially and fixed parts of FPGAs.