Defect Simulation Methodology for iDDT Testing
Journal of Electronic Testing: Theory and Applications
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Real-valued negative selection algorithm with a Quasi-Monte Carlo genetic detector generation
ICARIS'07 Proceedings of the 6th international conference on Artificial immune systems
Fault detection in analog circuits using a fuzzy dendritic cell algorithm
ICARIS'11 Proceedings of the 10th international conference on Artificial immune systems
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A technique for testing analog and mixed-signal linear circuit components based on their impulse response (IR) signatures is presented in this paper. A simple DFT structure is proposed to enable the on-chip generation of the impulse response signatures from the corresponding step responses of the circuit components. The proposed technique circumvents the need to apply pseudorandom patterns and perform complex on-chip cross-correlation for IR generation. A set of post processing steps based on cross/auto-correlation are proposed to efficiently compare IR signatures. A statistical approach based on linear regression and outlier analysis is used for defect screening. A continuous-time active state variable filter benchmark circuit is used as the Device-Under-Test as a means of validating this technique. The detection sensitivity for shorting and open resistive faults across various defect severity levels is analyzed. The detection results are compared and shown to be superior to a typical specification based test.