Specialized Hardware for Deep Network Packet Filtering
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Assisting Network Intrusion Detection with Reconfigurable Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Implementation of a Content-Scanning Module for an Internet Firewall
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Time and area efficient pattern matching on FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Deep Packet Filter with Dedicated Logic and Read Only Memories
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Scalable Pattern Matching for High Speed Networks
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Snort - Lightweight Intrusion Detection for Networks
LISA '99 Proceedings of the 13th USENIX conference on System administration
Fast Regular Expression Matching Using FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Compact state machines for high performance pattern matching
Proceedings of the 44th annual Design Automation Conference
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There has been a significant volume of recent work on reconfigurable designs for pattern matching at high data rates with large pattern sets. Although various pattern-matching architectures and implementations have been presented, attempts to compare different designs have been inconclusive, or even misleading, due to variations in testing procedures. There has been no general methodology for analyzing and comparing pattern-matching system design approaches. In this paper, we present a software toolset and an associated methodology that is then used to evaluate pattern-matching circuit performance. This evaluation framework relies on an analytical model of FPGA pattern-matching architectures that quantitatively expresses the relationships between pattern properties, circuit area, and circuit delay. Using our model and toolset, we show how the efficiency and performance of each architecture is dependent on certain properties of the pattern set. A number of experiments are performed to demonstrate that the model does indeed accurately represent the area and delay in FPGA implementations of the given architectures. For several architectures and multiple pattern sets, circuit netlists are generated and then compiled for the Xilinx Virtex II Pro platform. Our results show that pattern set properties such as pattern length and alphabet size impact the circuits of each pattern-matching architecture in markedly different ways. This indicates that useful insights are gained by using this model-based analysis methodology.