A 52mW 1200MIPS compact DSP for multi-core media SoC

  • Authors:

  • Shih-Hao Ou;Tay-Jyi Lin;Chao-Wei Huang;Yu-Ting Kuo;Chie-Min Chao;Chih-Wei Liu;Chein-Wei Jen

  • Affiliations:

  • National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan

  • Venue:
  • ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
  • Year:
  • 2006

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Abstract

This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive micro-architecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18μm 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.