Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design

  • Authors:
  • K. Hisamitsu;H. Ueno;M. Tanaka;D. Kitamaru;M. Miura-Mattausch;H. J. Mattausch;S. Kumashiro;T. Yamaguchi;K. Yamashita;N. Nakayama

  • Affiliations:
  • Graduate School of Advanced Sciences of Matter;Graduate School of Advanced Sciences of Matter;Graduate School of Advanced Sciences of Matter;Graduate School of Advanced Sciences of Matter;Graduate School of Advanced Sciences of Matter;Hiroshima University, Higashi-Hiroshima, Japan;Semiconductor Technology Academic Research Center, Kanagawa, Japan;Semiconductor Technology Academic Research Center, Kanagawa, Japan;Semiconductor Technology Academic Research Center, Kanagawa, Japan;Semiconductor Technology Academic Research Center, Kanagawa, Japan

  • Venue:
  • ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
  • Year:
  • 2003

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Abstract

The temperature-independence point (TIP) of the drain current for MOS transistors in a 0.1μm-scale pocket-implant technology is gate-length (Lg) dependent and has different magnitudes for n-MOSFET and p-MOSFET. Circuits such as ring-oscillators have a TIP, lying between the values for n- and p-MOSFET. The circuit TIP is close to the n-MOSFET TIP for long Lg and gets closer to the p-MOSFET TIP for short Lg. The reason is the different temperature dependence of electron and hole mobility as a function of Lg. Due to the high field effect, oscillation periods of ring-oscillators with short Lg hardly improve, when the supply voltage is raised beyond the TIP. Therefore, an advantageous supply-voltage (VDD) choice for pocket-implant technologies is near the TIP of circuits, allowing a favorable combination of short switching delay and minimized temperature dependence. By designing the Vth,p closer to Vth,n, not only the low power dissipation, due to the reduction of the TIP, but also the suppressed TIP fluctuation can be realized.