An image retrieval system using FPGAs

  • Authors:

  • Koji Nakano;Etsuko Takamichi

  • Affiliations:

  • School of Information Science, JAIST, Tatsunokuchi, Ishikawa, Japan;School of Information Science, JAIST, Tatsunokuchi, Ishikawa, Japan

  • Venue:
  • ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
  • Year:
  • 2003

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Abstract

The main contribution of this paper is to present an image retrieval system using FPGAs. Given a template image T and a database of a number of Images I1, I2,..., our system lists all images that contain a subimage similar to T. More specifically, a hardware generator in our system creates the Verilog HDL source of a hardware that determines whether Ii has a similar subimage to T for any image Ii and a particular template T. The created Verilog HDL source is embed in an FPGA using the design tool provided by the FPGA vendor. Since the hardware embedded in the FPGA is designed for a particular template T, it is an instance-specific hardware that allows us to achieve extreme acceleration. We evaluate the performance of our image matching hardware using a PCI-connected Xilinx FPGA and a timing analyzer. Since the generated hardware attains up to 3000 speed-up factor over the software solution, our approach is promising.