Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Testing of Quantum Dot Cellular Automata Based Designs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
Binary Adders on Quantum-Dot Cellular Automata
Journal of Signal Processing Systems
An information-theoretic analysis of quantum-dot cellular automata for defect tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time fault rates are expected to be quite high. Straightforward Triple Modular Redundancy (TMR) based fault tolerance is inappropriate for QCA nanotechnology since wire delays dominate the logic delays and faults in wires dominate the faults in a QCA based design. Furthermore, long wires are necessary in TMR based designs. In this paper we show that fault-tolerance can be obtained by using TMR with Shifted Operands (TMRSO). TMRSO uses shorter wires of QCA cells and exploits the self-latching property of clocked QCA arrays to provide the same level of fault tolerance capability as straightforward TMR while being significantly faster and smaller. This technique can be applied to a variety of operations; we have validated TMRSO on adders. Implementation results obtained using QCADesigner [6] show that an 8-bit adder using TMRSO has more than 50% area reduction and more than 100% throughput improvement when compared to a TMR implementation.