A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion

Authors:
K. Praveen Jayakar Thomas;Ram Singh Rana;Yong Lian
Affiliations:
National University of Singapore, Singapore;Institute of Microelectronics, Singapore;National University of Singapore, Singapore
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

A design and circuit implementation of a CMOS fourth-order continuous-time bandpass fs/4 sigma delta modulator is presented. The fully differential architecture of the modulator includes integrated LC resonators with active Q enhancement and return to zero, half return to zero latches to drive the feedback switched current source DACs. The modulator, designed for 0.18μm/1.8V 1P6M CMOS process occupies a total area of 1.8mm2 dissipating 290mW from a 1.8V power supply. At a sampling rate of 4GHz and a signal of 1GHz with 500kHz bandwidth, the circuit achieves a peak Signal-to-Noise and Distortion Ratio (SNDR) of 38dB. A CMOS implementation of the modulator provides the feasibility of integrating the following DSP circuits on the same chip in a RF receiver. This paper is aimed to provide a CMOS solution for RF signal of 1GHz range.