Continuous-time delta-sigma modulators for high-speed A/D conversion: theory, practice and fundamental performance limits
Metastability Requirements for a 2 GHz CMOS ΔΣ Modulator
ICSENG '05 Proceedings of the 18th International Conference on Systems Engineering
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
CMOS Current Amplifiers: Speed versus Nonlinearity
CMOS Current Amplifiers: Speed versus Nonlinearity
IEEE Communications Magazine
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This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm2.