An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters
Analog Integrated Circuits and Signal Processing
ASF: a practical simulation-based methodology for the synthesis of custom analog circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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This paper describes an automated device sizing system for current-steering D/A converters (DACs) and an 11-bit 160-MS/s DAC implemented using this system. Based on an analysis of harmonic distortion (or spurious) of the DAC, a circuit technique named One-Vgs Switching has been newly developed for realizing high spurious free dynamic range (SFDR). The automated device sizing system has also been developed for quick retargeting of the current-steering DAC. The 11-bit 160-MS/s DAC has been designed using this system and fabricated in a 0.18-μm technology. It operates at 1.35-V power supply with 10-mW power consumption, 1.6-Vppd output swing, and 61-dB SFDR at fsig=10.2 MHz. Its active area is 0.22 mm2.